1. Field of the Invention
The present invention generally relates to a self-aligned non-volatile memory and method of manufacture and more particularly relates to a triple-self-aligned split gate non-volatile random access memory (NVRAM) cell.
2. Description of the Related Art
Non-volatile semiconductor memory cell using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the scale of integration of semiconductor processing increases, reducing the largest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing.
In view of the foregoing and other problems of the conventional methods and processes, an object of this invention is to achieve the manufacturing of a semiconductor memory array of a floating gate memory cell array.
It is also an object of the present invention to provide a non-volatile RAM cell including a plurality of polysilicon floating gates, each having a sharp tip, a first side, a top side and a second side. The sharp tip of the floating gate may be formed at a junction of the top side and the second side. An insulator spacer may be provided on a portion of the top side and on the first side of each of the floating gates. A self-aligned contact (i.e., such as a polysilicon source line contact plug) may be provided between adjacent floating gates. A dielectric material may be provided on another portion of the top side, on the sharp tip and on the second side of each of the floating gates. A polysilicon wordline spacer may also be provided on one side of the insulator spacer and over the dielectric material.
In the present invention, self-aligned methods are disclosed to form a semiconductor memory array of floating gate memory cells of the split gate type as well as such memory arrays formed thereby. In the self aligned method of the present invention, the memory cell may have a first terminal, a second terminal with a channel between the first terminal and the second terminal, a floating gate, and a control gate. A plurality of spaced isolation regions may be formed in the substrate. The isolation regions may be substantially parallel to one another in a first direction with an active region between each pair of adjacent isolation regions. Each active region may have a first layer of insulating material on the semiconductor substrate, and a first layer of polysilicon material on the first layer of the insulating material. A plurality of spaced apart masking regions of a masking material are formed substantially parallel to one another on the semiconductor substrate in a second direction crossing a plurality of alternating active regions and isolation regions. The second direction may be substantially perpendicular to the first direction. A plurality of spaced apart first spacers of an insulating material may be formed substantially parallel to one another in the second direction. Each of the first spacers may be adjacent to and contiguous with one of the masking regions with a first region between each pair of adjacent first spacers. Each first spacer may cross a plurality of alternating active regions and isolation regions. The material may be etched between each pair of adjacent first spacers in the first region. A first terminal may be formed in the substrate in the active region between pairs of adjacent first spacers in the first region. A conductor may be formed in the second direction between each pair of spaced apart first spacers, electrically connected to the first terminal in the substrate.
The masking material may be removed resulting in a plurality of spaced apart structures substantially parallel to one another in the second direction. An insulating film may be formed about each of these structures. A plurality of spaced apart second spacers of polysilicon material substantially parallel to one another may be formed in the second direction. Each second spacer may be adjacent to and contiguous with one of the structures. A second region may be between each pair of adjacent second spacers with each second spacer crossing a plurality of alternating active regions and isolation regions. Each of the second spacers may electrically connect the control gates for the memory cells in the second direction. Between each pair of adjacent second spacers in the second region, the material may be etched. A second terminal may be formed in the substrate in each of the active regions between pairs of adjacent second spacers in the second region. Finally, a conductor may be formed in a first direction substantially parallel to an active region and electrically connected to the second terminals in the first direction.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.